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author | Jack Leightcap <jack@leightcap.com> | 2023-08-04 23:06:35 -0400 |
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committer | Jack Leightcap <jack@leightcap.com> | 2023-08-04 23:06:35 -0400 |
commit | eb2222a132e3d533825d855594ee7f0d8f84bc31 (patch) | |
tree | ea06c032fdf8c6aa295909417ad2b449dbd6e55f /pkgs | |
parent | 84935de73ed64fdd258f0791e993e8e71af1e25f (diff) | |
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fixup! python3Packages.cocotb: 1.7.2 -> 1.8.0
Signed-off-by: Jack Leightcap <jack@leightcap.com>
Diffstat (limited to 'pkgs')
-rw-r--r-- | pkgs/development/python-modules/cocotb/default.nix | 25 |
1 files changed, 18 insertions, 7 deletions
diff --git a/pkgs/development/python-modules/cocotb/default.nix b/pkgs/development/python-modules/cocotb/default.nix index 10034b052d55..cd9c3b035819 100644 --- a/pkgs/development/python-modules/cocotb/default.nix +++ b/pkgs/development/python-modules/cocotb/default.nix @@ -1,5 +1,16 @@ -{ lib, stdenv, buildPythonPackage, fetchFromGitHub, setuptools, setuptools-scm -, cocotb-bus, find-libpython, pytestCheckHook, swig, verilog }: +{ lib +, stdenv +, buildPythonPackage +, fetchFromGitHub +, setuptools +, setuptools-scm +, cocotb-bus +, find-libpython +, pytestCheckHook +, swig +, verilog +, ghdl +}: buildPythonPackage rec { pname = "cocotb"; @@ -10,7 +21,7 @@ buildPythonPackage rec { owner = "cocotb"; repo = "cocotb"; rev = "refs/tags/v${version}"; - hash = "sha256-gLOYwljqnYkGsdbny7+f93QgroLBaLLnDBRpoCe8uEg="; + hash = "sha256-k3VizQ9iyDawfDCeE3Zup/KkyD54tFBLdQvRKsbKDLY="; }; nativeBuildInputs = [ setuptools-scm ]; @@ -42,7 +53,7 @@ buildPythonPackage rec { ./0001-Patch-LDCXXSHARED-for-macOS-along-with-LDSHARED.patch ]; - nativeCheckInputs = [ cocotb-bus pytestCheckHook swig verilog ]; + nativeCheckInputs = [ cocotb-bus pytestCheckHook swig verilog ghdl ]; preCheck = '' export PATH=$out/bin:$PATH mv cocotb cocotb.hidden @@ -51,10 +62,10 @@ buildPythonPackage rec { pythonImportsCheck = [ "cocotb" ]; meta = with lib; { - description = - "Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python"; + changelog = "https://github.com/cocotb/cocotb/releases/tag/v${version}"; + description = "Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python"; homepage = "https://github.com/cocotb/cocotb"; license = licenses.bsd3; - maintainers = with maintainers; [ matthuszagh ]; + maintainers = with maintainers; [ matthuszagh jleightcap ]; }; } |