Merge master into staging-next

2 files changed, 139 insertions, 0 deletions

diff --git a/pkgs/development/compilers/yosys/plugins/synlig-makefile-for-nix.patch b/pkgs/development/compilers/yosys/plugins/synlig-makefile-for-nix.patch
new file mode 100644
index 000000000000..7d1f407d6fdc
--- /dev/null
+++ b/pkgs/development/compilers/yosys/plugins/synlig-makefile-for-nix.patch
@@ -0,0 +1,66 @@
+diff --git a/Makefile b/Makefile
+index 4c96ae7..9e1a2e3 100755
+--- a/Makefile
++++ b/Makefile
+@@ -3,7 +3,7 @@
+ # Setup make itself.
+ 
+ .ONESHELL:
+-override SHELL := /bin/bash
++SHELL := bash
+ override .SHELLFLAGS := -e -u -o pipefail -O nullglob -O extglob -O globstar -c
+ 
+ # Unset all default build- and recipe-related variables.
+@@ -315,7 +315,6 @@ endif
+ GetTargetStructName = target[${1}]
+ 
+ makefiles_to_include := \
+-	third_party/Build.*.mk \
+ 	frontends/*/Build.mk \
+ 	tests/*/Build.mk \
+ 	lib/*/Build.mk
+diff --git a/frontends/systemverilog/Build.mk b/frontends/systemverilog/Build.mk
+index acd9cb6..c039994 100644
+--- a/frontends/systemverilog/Build.mk
++++ b/frontends/systemverilog/Build.mk
+@@ -1,6 +1,7 @@
+ t       := systemverilog-plugin
+ ts      := $(call GetTargetStructName,${t})
+ out_dir := $(call GetTargetBuildDir,${t})
++mod_dir := third_party/yosys_mod
+ 
+ cxx_is_clang := $(findstring clang,$(notdir ${CXX}))
+ 
+@@ -13,9 +14,9 @@ ${ts}.sources := \
+ 	${${ts}.src_dir}uhdm_ast_frontend.cc \
+ 	${${ts}.src_dir}uhdm_common_frontend.cc \
+ 	${${ts}.src_dir}uhdm_surelog_ast_frontend.cc \
+-	${$(call GetTargetStructName,yosys).mod_dir}const2ast.cc \
+-	${$(call GetTargetStructName,yosys).mod_dir}edif.cc \
+-	${$(call GetTargetStructName,yosys).mod_dir}simplify.cc
++	$(mod_dir)/const2ast.cc \
++	$(mod_dir)/edif.cc \
++	$(mod_dir)/simplify.cc
+ 
+ define ${ts}.env =
+ export PKG_CONFIG_PATH=$(call ShQuote,${$(call GetTargetStructName,surelog).output_vars.PKG_CONFIG_PATH}$(if ${PKG_CONFIG_PATH},:${PKG_CONFIG_PATH}))
+@@ -35,8 +36,8 @@ endif
+ endif
+ 
+ ${ts}.cxxflags = \
+-	-I${$(call GetTargetStructName,yosys).src_dir} \
+-	-I${$(call GetTargetStructName,yosys).mod_dir} \
++	-I$(shell yosys-config --cxxflags) \
++	-I$(mod_dir) \
+ 	-D_YOSYS_ \
+ 	-DYOSYS_ENABLE_PLUGINS \
+ 	$(shell ${${ts}.env}; pkg-config --cflags Surelog) \
+@@ -55,7 +56,7 @@ ${ts}.ldflags = \
+ 	$(shell ${${ts}.env}; pkg-config --libs-only-L Surelog) \
+ 	${build_type_ldflags} \
+ 	${LDFLAGS} \
+-	-Wl,--export-dynamic
++	$(shell yosys-config --ldflags --ldlibs)
+ 
+ ${ts}.ldlibs = \
+ 	$(shell ${${ts}.env}; pkg-config --libs-only-l --libs-only-other Surelog) \
diff --git a/pkgs/development/compilers/yosys/plugins/synlig.nix b/pkgs/development/compilers/yosys/plugins/synlig.nix
new file mode 100644
index 000000000000..ccbf88159313
--- /dev/null
+++ b/pkgs/development/compilers/yosys/plugins/synlig.nix
@@ -0,0 +1,73 @@
+{ stdenv
+, lib
+, fetchFromGitHub
+, pkg-config
+, antlr4
+, capnproto
+, readline
+, surelog
+, uhdm
+, yosys
+}:
+
+stdenv.mkDerivation (finalAttrs: {
+  pname = "yosys-synlig";
+  version = "2023.10.12";  # Currently no tagged versions upstream
+  plugin = "synlig";
+
+  src = fetchFromGitHub {
+    owner  = "chipsalliance";
+    repo   = "synlig";
+    rev    = "c5bd73595151212c61709d69a382917e96877a14";
+    sha256 = "sha256-WJhf5gdZTCs3EeNocP9aZAh6EZquHgYOG/xiTo8l0ao=";
+    fetchSubmodules = false;  # we use all dependencies from nix
+  };
+
+  patches = [
+    ./synlig-makefile-for-nix.patch  # Remove assumption submodules available.
+  ];
+
+  nativeBuildInputs = [
+    pkg-config
+  ];
+
+  buildInputs = [
+    antlr4.runtime.cpp
+    capnproto
+    readline
+    surelog
+    uhdm
+    yosys
+  ];
+
+  buildPhase = ''
+    runHook preBuild
+    make -j $NIX_BUILD_CORES build@systemverilog-plugin
+    runHook postBuild
+  '';
+
+  # Very simple litmus test that the plugin can be loaded successfully.
+  doCheck = true;
+  checkPhase = ''
+     runHook preCheck
+     yosys -p "plugin -i build/release/systemverilog-plugin/systemverilog.so;\
+               help read_systemverilog" | grep "Read SystemVerilog files using"
+     runHook postCheck
+  '';
+
+  installPhase = ''
+    runHook preInstall
+    mkdir -p $out/share/yosys/plugins
+    cp ./build/release/systemverilog-plugin/systemverilog.so \
+           $out/share/yosys/plugins/systemverilog.so
+    runHook postInstall
+  '';
+
+  meta = with lib; {
+    description = "SystemVerilog support plugin for Yosys";
+    homepage    = "https://github.com/chipsalliance/synlig";
+    license     = licenses.asl20;
+    maintainers = with maintainers; [ hzeller ];
+    platforms   = platforms.all;
+  };
+})