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| author | Sandro <sandro.jaeckel@gmail.com> | 2023-06-19 14:14:03 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-06-19 14:14:03 +0200 |
| commit | 9a670fec3ba7fed22112fc6abec8f7aa62db331b (patch) | |
| tree | fd64f931cc1d36cb6d1560544f480fcb43a104a6 /lib | |
| parent | 8d5c9d3462142ef5bcea31012d1e94e59f9bd831 (diff) | |
| parent | a41e973062ddc4b0d1d43f1e11dfa25f0068d2a2 (diff) | |
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Merge pull request #237167 from CHN-beta/master
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/systems/architectures.nix | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/systems/architectures.nix b/lib/systems/architectures.nix index f8cf0e2b933f..11668ae59a71 100644 --- a/lib/systems/architectures.nix +++ b/lib/systems/architectures.nix @@ -18,6 +18,7 @@ rec { cascadelake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; cooperlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; tigerlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ]; + alderlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "fma" ]; # x86_64 AMD btver1 = [ "sse3" "ssse3" "sse4_1" "sse4_2" ]; btver2 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ]; @@ -56,6 +57,8 @@ rec { cascadelake = [ "skylake-avx512" ] ++ inferiors.cannonlake; cooperlake = [ "cascadelake" ] ++ inferiors.cascadelake; tigerlake = [ "icelake-server" ] ++ inferiors.icelake-server; + # CX16 does not exist on alderlake, while it does on nearly all other intel CPUs + alderlake = [ ]; # x86_64 AMD # TODO: fill this (need testing) |